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Parent target name of the current target in GNU Makefile


By : Mukesh Maheshwari
Date : October 14 2020, 02:22 PM
this will help What you are probably looking for is Target-specific Variable Values. If you carefully read this section of the manual you'll see how they propagate to the prerequisites.
Just to illustrate how they work:
code :
.PHONY: all release debug compile

all:
    $(MAKE) release
    $(MAKE) debug

release: CXXFLAGS = for rel
debug: CXXFLAGS = for deb

release debug: compile
    @echo 'building $@ with CXXFLAGS = $(CXXFLAGS)'

compile: a b c
    @echo 'building $@ with CXXFLAGS = $(CXXFLAGS)'

a b c:
    @echo 'building $@ with CXXFLAGS = $(CXXFLAGS)'
$ make --no-print-directory all
make release
building a with CXXFLAGS = for rel
building b with CXXFLAGS = for rel
building c with CXXFLAGS = for rel
building compile with CXXFLAGS = for rel
building release with CXXFLAGS = for rel
make debug
building a with CXXFLAGS = for deb
building b with CXXFLAGS = for deb
building c with CXXFLAGS = for deb
building compile with CXXFLAGS = for deb
building debug with CXXFLAGS = for deb


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How do you conditionally call a target based on a target variable (Makefile)?


By : Andrew Harry
Date : March 29 2020, 07:55 AM
it helps some times It's not at all clear that what you're asking for is really what you want, but here goes:
code :
all:

ifeq ($(BUILD_ENV),development)
all: clean-dev
else
all: clean-other
endif

clean-dev:
    @echo running $@, doing something

clean-other:
    @echo running $@, doing something else

Makefile target with wildcard to create symlink using target string


By : Sanam Khatri
Date : March 29 2020, 07:55 AM

Makefile always says generated-file target is up to date, but generates target as expected


By : Leonardo
Date : March 29 2020, 07:55 AM
Hope this helps I have a script that, when run, generates a file. I want to create a Makefile to run the script to generate the file if the generated file does not exist or if the script changes. ,
When I run make, I see the following output:
code :
make: '/workspace/sw/bhshelto/temp/makefile_test/genfile.foo' is up to date.

C++ How would I combine two makefile object target rules (which are located in another folder) into one target/rule?


By : user1736891
Date : March 29 2020, 07:55 AM
I wish this helpful for you My C++ program consists of three files: , You need to change:
code :
OBJECTS = ./bin/main.o \
          ./bin/hellolib.o
OBJECTS = bin/main.o \
          bin/hellolib.o
./bin/%.o : src/%.cpp
        $(CC) -c $< -o $@
SOURCES = src/main.cpp \
          src/hellolib.cpp

OBJECTS = $(patsubst src/%.cpp,bin/%.o,$(SOURCES))

Target dependency: Makefile no rule to make target error


By : user3597202
Date : March 29 2020, 07:55 AM
it should still fix some issue This means make cannot find a file named $(OUTPUTDIR)/%.cpp, a prerequisite for the first rule.
You cannot use % as a wildcard anywhere in a rules like this:
code :
 build: pre_build_script $(OUTPUTDIR)/%.cpp
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